1. Field of the Invention
The embodiments of the invention generally relate to testing and analyzing microelectronic devices, and more particularly to integrated circuit (IC) diagnostic techniques used during IC fabrication and processing.
2. Description of the Related Art
Missing, incorrect, or over/under processing of individual manufacturing steps are common problems in the semiconductor industry, especially when new process technologies are under development. Fast discovery of the root cause(s) of these problems and immediate correction is therefore a key to success in this competitive industry. These mis-processed semiconductor steps (for example, missing halo implant) manifest different device performance characteristics, and are often difficult or even impossible to locate with particularity (i.e., pin point) without exhaustive and expensive failure analysis diagnostic techniques and/or time consuming engineering wafer split lot experiments, which ultimately compare electrical performance of intentionally mis-processed to correctly processed wafers.
The areas between the actual chips on a semiconductor wafer that eventually get destroyed during dicing are called “kerfs” or “streets”. Typically, semiconductor manufacturers place easily testable circuit and device structures in the area between individual chips on a wafer (i.e., the “kerf”), but usually such structures are robustly designed, and are tailored to device engineering needs. In addition, these kerf structures receive the identical processing as the entire wafer (correctly or incorrectly), since the kerf is intended to supply device and circuit characteristics to predict the actual chip performance and yield. However, currently the kerf is not designed, intended, and is rarely used as a “diagnostic failure analysis” tool. Manufacturers use the kerf area to place numerous circuits for the purpose of testing and monitoring the health of the processing as the wafers go through the line. Many types of transistors, resistors, capacitors, inductors, and logic and analog circuits thereof are configured to measure myriad parameters like sheet resistance, contact resistance, insulator capacitance, threshold voltage, leakage, defect density, line widths, junction depths, etc. These circuits are wired to relatively large metal pads that are probed by testers at various points during manufacture in a process called “inline test.”
The monitor circuits above require that the semiconductor processing be of sufficient quality that the monitors themselves are functional, and able to detect more subtle processing errors. In other words, if entire layers are missing, or significantly out of “spec” (specification), then the circuit cannot monitor normal process variations and subtle problems, and diagnosing these gross errors is made even more difficult.
Without the aid of the monitor circuits, the only known methods for diagnosing the gross errors described above are running expensive and time-consuming experiments in an attempt to duplicate the problem under known processing conditions, and expensive “brute-force” laboratory inspection using high-sensitivity instrumentation in a slow and often dead-end “shotgun” approach.
Moreover, with most current failure analysis techniques and available electrical test information, definitive diagnosis typically cannot be achieved without months of long and costly engineering split lot experiments. Moreover, even then, the engineering split lot experiment selection may be incorrect, thereby yielding unusable diagnostic information, thus requiring additional split lots.
U.S. Pat. No. 6,797,981 (“the '981 patent”) incorporated herein by reference uses purposely “designed-in” errors to test semiconductor wafers. However these errors are meant to mimic “random” process defects (foreign material, localized extra or missing shapes) that affect only very small and localized areas of a chip and are detectable using known diagnostic methods. The '981 patent is a way to test those known diagnostic methods in a systematic way. However, when entire levels or process steps are missing in a wafer, all known diagnostic methods are generally rendered useless. Hence, there is a need to allow one to diagnose very gross process errors when entire levels or process steps are missing in a wafer and/or the associated circuitry.
Thus, the conventional techniques generally fail to provide an adequate and timely diagnostic failure analysis/technique. Therefore, there remains a need for a novel inexpensive diagnostic technique used in testing an element of a semiconductor manufacturing process.